`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/29 22:54:47
// Design Name: 
// Module Name: test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test(
    clk,addr,addr_ir,op_pc,offset
);
    input clk;
    input [1:0] op_pc;
    input [31:0] addr,offset;
    output reg [31:0] addr_ir;

    wire [31:0] ad;
    
    assign ad = addr + (op_pc ? 32'b100 : offset);
    

    always @(posedge clk) begin
        addr_ir <= ad;
    end 
endmodule

